Verilog grammar for tree-sitter
Syntax highlighting for Verilog, powered by WebAssembly
Verilog language support for CodeMirror 6
My verilog LSP parser for vscode-verilog plugin
Verilog import / export package
Verilog exporter for Runiq digital circuits
Verilog language support for syntastica-js
Theia - Verilog Extension
extract pinlist from verilog files
Simten simulator engine, circuit IR builder, standard library, and Verilog exporter. Pure TypeScript with no browser dependencies.
auto verilog from comments
AI-powered Verilog editor for rapid FPGA bitstream generation
这是一个Verilog的扩展
A Visual Studio Code extension for compiling Verilog modules with Iverilog and simulating results with GTKWave.
build a parts list for a verilog module
Adds support for the Verilog in Brackets text editor
Lattice iCE40 Verilog project.
Create Verilog test benches from asynchronous tests generated by BreezeTestGen.
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SystemVerilog 1800-2023 Parser
A language server for systemverilog
Export Yosys netlists to a logic simulator
Verilog preprocessor
OpenClaw diffs viewer syntax highlighting language pack
Parser for Verilog.
surge synthesizer -- lfos used for modulation
A proc-macro to wrap Verilog code in a rust-hdl module
Binary that integrates XLS capabilities into a driver program
Verilog AST + emitter for hdl-cat IR graphs
Verilog grammar for arborium (tree-sitter bindings)
Verilog language parser with support for modern Verilog syntax and features.
Parser for structural verilog as it is created by Yosys.
A library to parse a Verilog Filelist and return a list of files, include directories and defines
SystemVerilog language server
Verilog grammar for tree-sitter
Umbrella crate re-exporting the hdl-cat workspace
File helpers with specific functions for Verilog HDL
A parser and generator for Verilog (IEEE 1364)
Extension to the verilog gem, adds rename functionality and updates instatiations
Verilog write plugin for RgGen
Writing portable RTL design in verilog is challenging due to limitations of verilog language. Hence would like to write the leaf modules of the design in verilog but use Ruby to stich different views of the design.
Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI and a platform for unit testing, rapid prototyping, and systems integration of Verilog modules through Ruby. It lets you create complex Verilog test benches easily and wholly in Ruby.
Simple assembler written in Ruby for a simple 16-bit CPU written in Verilog.
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